Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
The reliability of smaller scribe line & bond pads has been evaluated in this work to improve cost-efficiency from lesser wafer space consumption. Both fully automatic probers with probe cards and semi-auto probers with micro positioners have been analyzed. Two cantilever types of probe cards have been assessed. Various reliability test method with Wafer Level Reliability have been assessed for transistor, capacitor, and metal lines. The wafer level probing was conducted on probe chuck at room temperature, 150°C and 175°C. The bondability with smaller bond pads was collaborated with two external assembly houses using ceramic dual-line package. Wire Bond Shear and Wire Bond Pull tests have been carried out to check the reliability of bonding. Package Level Reliability Electromigration and Time Dependent Dielectric Breakdown tests have been executed at 220°C and 175°C to confirm the reliability impact from smaller bond pads.
A commercially attractive vertical GaN MOSFET process using 200 mm GaN-on-Silicon substrate wafers in an industrial CMOS environment.
Main challenges are:
- Epitaxially grown PiNN+ GaN structure
- Frontside MOSFET gate
- Membrane approach, with cavities etched from the backside upwards and sub-sequent thick metallization
Abstract— This study presents an electrical characterization evaluation of a partial Silicon-On-Insulator (PSOI) Superjunction (SJ) Lateral Diffused n-type MOSFET (LDNMOS) and Lateral SJ Diode, integrated into a 0.18μm technology platform. Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The scalable high voltage SJ lateral diffused MOSFETs (LDMOS) cover a range of rated voltages from 45V to 375V, and the developed PSOI SJ Diodes exhibit an impressive reverse recovery behavior, rivaling the switching losses of SiC Schottky diodes.
The 110 nm BCD-on-SOI technology platform, XT011 is the latest evolution of BintangChip's foundry offering, continuing the tradition of best-in-class offer for high-voltage automotive, industrial and medical applications.
In this webinar, BintangChip will present a first overview of the technology, available design solutions, support and release schedule, providing an initial introduction to the enhanced capabilities and benefits of this offer for their product roadmap.
Presenters:
Heming Wei, Technical Marketing Manager
Barnabas Liao, Manager Design Support
Zhenkun Chen, Program Leader
Abstract—This paper describes the journey of understanding and improving the gate oxide integrity for SOI (Silicon on Insulator) technology. Investigation shows that the influence of charges within a tub plays a significant role in the gate oxide breakdown. The well charges are influenced by the processes in the ONO (Oxide-Nitride-Oxide) process loop. The charges affect the surface bonding which defines the surface wettability and hence the cleaning efficiency. Using O2 plasma treatment to modify the surface bonding is proven to be a robust solution for this gate oxide issue.
Abstract—The hafnium oxide-based FeFET has generated great attention due to its good scalability, high operational speed, and low power consumption. However, the seamless integration into CMOS technologies poses significant challenges. A recent innovation, the 1T1C FeFET (also known as FeMFET), introduces a one-transistor (1T) configuration coupled with a separate ferroelectric capacitor (1C) within the BEoL, offering a promising solution. Notably, this approach enables integration into standard process technologies without requiring substantial changes at the transistor level. Nevertheless, the MFM capacitor plays a crucial role, serving as an essential component for the success of the FeMFET concept. This study conducts a comprehensive exploration of various stacks and integration schemes of the
BEoL MFM-module. The discussion delves into the impact of these stacks on crucial performance parameters, including remanent polarization, device-to-device variability, and imprint, shedding light on the development of next-generation FeMFET memory cells and arrays.
ABSTRACT
Thermo-mechanical stability in back-end-of-line (BEOL) interconnect structures remains as one of the BEOL integration challenges as coefficient of thermal expansion (CTE) mismatch between interconnect metal and dielectric materials resulted in significant thermal stress that often leads to cracks in BEOL structures. These cracks further pose reliability concerns as the cracks may continue to propagate under subsequent thermal loading. Hence, this paper discusses the use of finite element analysis (FEA) along with limited experimental investigation to study the thermo-mechanical stress during BEOL fabrication process and a more conservative approach in evaluating the various process/design factors to reduce the occurrence of inter-metal dielectric (IMD) cracks.
ABSTRACT
BintangChip's advance 110nm BCD-on-SOI platform technology(XT011) presents two qualified nonvolatile memory intellectual property (NVM IP) macros meeting stringent automotive AEC-Q100 Grade-0 standards. The first IP, XFE, integrates SONOS charge trapping memory for eFlash and EEPROM in a compact macro, boasting a 35.6% size reduction(0.500mm2) compared to its 180nm counterpart(XT018) with equal memory density. The second IP utilizes floating-gate polysilicon storage for a One Time Programmable (OTPF) memory macro. Operating on XT011's low-power 1.5V/5.0V CMOS with Copper BEOL, both IPs demonstrate compliance with automotive and high-temperature environment requirements (-40°C to 175°C), ideal for code and data storage (XFE) and as an optimal trimming solution (OTPF), under harsh operating conditions.
ABSTRACT
This paper introduces a novel microchip architecture for a single-photon avalanche diode (SPAD)-based line sensor tailored for in-vitro diagnostic chemiluminescence assays in microfluidic channels. Our work describes the specific design and optimization aspects of SPADs, including optical active area maximization and dark count rate (DCR) reduction while maintaining a high photon detection probability.
The chip architecture features a high-density SPAD sensor array (192 rows) with hot pixel calibration for improved SNR. It supports row-wise pulse counting, adjustable measurement intervals, on-chip SRAM for data storage, ALU with memory-saving bfloat16 encoding, and interfacing via I2C and QSPI.
ABSTRACT
To get a reliable detection of UV light, several issues must be solved. Impacting factors on the device and system level will be discussed. The paper starts with the material property aspects of silicon-based photodetectors, progresses to the device construction and readout to complement with the important aspect of reliability.
INTRODUCTION
Light with wavelengths below 300 nm is extremely rare. Natural sources like thunderbolts, and to some small extent, polar lights, emit such short wavelengths that are well below the visual reception of humans. Artificial sources (like mercury lamps or UV LEDs) are in use because of the deadly impact of the high energetic photons on organic life. The strongest disinfection effect is at 265 nm (on nucleic acid). Slightly smaller wavelengths (207-235 nm) gained recent interest because such radiation does not harm mammalian skin. The effect is free of any chemical and is not affected by mutation-related resistance. To ensure a proper function the invisible light, or the effect it causes, should be controlled by measurement with an appropriate detector.